A heterojunction MES-type field effect transistor is a potential candidate for high-speed applications because electrons traveling along an active channel layer suffer less ionized-impurity scattering. A typical example of the heterojunction MES-type field effect transistor is illustrated in FIG. 1 of the drawings. The heterojunction field effect transistor illustrated in FIG. 1 is fabricated on a semi-insulating gallium-arsenide substrate 1. On the semi-insulating gallium-arsenide substrate 1 is grown an undoped gallium-arsenide layer 2 which is overlain by an n-type aluminum-gallium-arsenide layer 3, then a heterojunction takes place between the undoped gallium-arsenide layer 2 and the n-type aluminum-gallium-arsenide layer 3 due to difference in bandgap therebetween. Donor impurity atoms are doped into the n-type aluminum-gallium-arsenide layer 3 and the undoped gallium-arsenide layer 2 to form source and drain regions 4 and 5 on which source and drain electrodes 6 and 7 of a gold-germanium-nickel alloy are formed to provide ohmic contacts therebetween. Over that area between the source and drain regions 4 and 5 formed in the n-type aluminum-gallium-arsenide layer 3 is provided a gate electrode 8 of aluminum which is biased to control an active channel layer formed in the undoped gallium-arsenide layer 2 underneath the heterojunction between the undoped gallium-arsenide layer 2 and the n-type aluminum-gallium-arsenide layer 3. In the active channel layer, electrons are moved from the source region 4 to the drain region 5 due to difference in voltage level between the source and drain regions 4 and 5, so that a switching speed of the heterojunction field effect transistor depends upon the transit time of the electrons traveling under the gate electrode 8. For this reason, attempts are made for reduction in gate length of the heterojunction field effect transistor so as to improve the switching speed of the transistor. The word "length" is hereinunder measured in the direction between the source and drain regions of a field effect transistor.
However, a problem is encountered in saturation of the transit time when the gate is decreased in length over a certain value. This is because of the fact that the electrons are insufficiently accelerated during the traveling over the extremely short channel.
Another example is disclosed by Mimura in U.S. Pat. No. 4,424,525 and the structure disclosed therein is similar to that illustrated in FIG. 1, so that the heterojunction device disclosed in the above U.S. patent will have the problem described hereinbefore if the gate is reduced in length over the certain value.